1. Field of the Invention
The present invention relates to a data detector for a counter.
2. Related Background Art
In the past, when a clock signal is to be counted to detect data thereof, synchronous counters having a 4-bit output such as TTL 74LS169 and D flip-flops having a common clock such as TTL 74LS373 are usually used, as shown in FIG. 5, in which numeral 65 denotes a clock signal, numeral 66 denotes a latch signal, numerals 63 and 64 denote D flip-flops, and numerals 61 and 62 denote synchronous counters having a 4-bit output. A common clock is used for lower order and higher order synchronous counters 61 and 62, and a carry signal of the lower order counter 61 is used as an enable signal to the higher order counter 62.
However, where such synchronous counters are used, it is necessary that the carry signal serially goes through from the lower order to the higher order during the counted clock period. Therefore, as the number of stages increases, the countable frequency f count is lowered. ##EQU1## where t.sub.pd1 : Clock.fwdarw.ripple carry
t.sub.pd2 : Enable T.fwdarw.ripple carry PA1 n: number of stages connected (number of IC's)
If a clock having a higher frequency than f count is applied, next clock is inputted before the high order bit is enabled. Therefore, it is not counted by the higher order counter and the carry to the high order bit is not effected. On the other hand, in an asynchronous counter, an input to one bit is an output from the immediately lower order bit. Accordingly, the high order bit is produced after the low order bit but no malfunction occurs unless a maximum frequency of the counter is exceeded. However, in the asynchronous counter, if data of the counter is detected in the course of carry from the low order bit to the high order bit, the data prior to the carry of the high order bit is detected.